ML Anthology

Design of Fast Connected Components Hardware

Xue Dong Yang
CVPR 1988 pp. 937-944
doi:10.1109/CVPR.1988.196345 /cvpr/1988/yang1988cvpr-design/

Abstract

The intensive use of the connected components algorithms in image analysis and robot vision calls for a very fast implementation of such algorithms suitable for real-time applications. A hardware design is presented which implements the algorithm due to J.T. Schwartz, M. Sharir, and A. Siegel (1985). A prototype board, which does not use special VLSI chips, had been constructed previously that can compute the connected components in a 512*512 binary image in few video frame times (about 300 ms). A real-time version (video speed) in VLSI is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

PDF CVPR Semantic Scholar

Cite

Text

Yang. "Design of Fast Connected Components Hardware." IEEE/CVF Conference on Computer Vision and Pattern Recognition, 1988. doi:10.1109/CVPR.1988.196345

Markdown

[Yang. "Design of Fast Connected Components Hardware." IEEE/CVF Conference on Computer Vision and Pattern Recognition, 1988.](https://mlanthology.org/cvpr/1988/yang1988cvpr-design/) doi:10.1109/CVPR.1988.196345

BibTeX

@inproceedings{yang1988cvpr-design,
  title     = {{Design of Fast Connected Components Hardware}},
  author    = {Yang, Xue Dong},
  booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition},
  year      = {1988},
  pages     = {937-944},
  doi       = {10.1109/CVPR.1988.196345},
  url       = {https://mlanthology.org/cvpr/1988/yang1988cvpr-design/}
}