ML Anthology

Computer Vision Hardware Using the Radon Transform

W. B. Baringer, Robert W. Brodersen, Dragutin Petkovic
CVPR 1991 pp. 508-513
doi:10.1109/CVPR.1991.139744 /cvpr/1991/baringer1991cvpr-computer/

Abstract

A highly integrated VME-based board (based on parallel pipeline projection engine, PPPE, architecture) containing custom VLSI application-specific ICs (ASICs) that implements the forward and inverse Radon transforms in real time has been designed and fabricated. The board contains DSP microcomputers (AT&T DSP32C) that provide the necessary modularity and programming power to support custom Radon-transform ASICs. Parallel and pipelined processing occurs at both the IC and the board level. The ASIC that executes the highly computational- and I/O-intensive forward and inverse Radon transform algorithms has been designed and fabricated in a 1.6-micron scalable CMOS process. It operates at the required 10-MHz video rate, and consists of over 120000 transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

CVPR Semantic Scholar

Cite

Text

Baringer et al. "Computer Vision Hardware Using the Radon Transform." IEEE/CVF Conference on Computer Vision and Pattern Recognition, 1991. doi:10.1109/CVPR.1991.139744

Markdown

[Baringer et al. "Computer Vision Hardware Using the Radon Transform." IEEE/CVF Conference on Computer Vision and Pattern Recognition, 1991.](https://mlanthology.org/cvpr/1991/baringer1991cvpr-computer/) doi:10.1109/CVPR.1991.139744

BibTeX

@inproceedings{baringer1991cvpr-computer,
  title     = {{Computer Vision Hardware Using the Radon Transform}},
  author    = {Baringer, W. B. and Brodersen, Robert W. and Petkovic, Dragutin},
  booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition},
  year      = {1991},
  pages     = {508-513},
  doi       = {10.1109/CVPR.1991.139744},
  url       = {https://mlanthology.org/cvpr/1991/baringer1991cvpr-computer/}
}