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Hardware Implementation of an SAD Based Stereo Vision Algorithm

Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger, Andreas Steininger
CVPR 2007
doi:10.1109/CVPR.2007.383417 /cvpr/2007/ambrosch2007cvpr-hardware/

Abstract

This paper presents the hardware implementation of a stereo vision core algorithm, that runs in real-time and is targeted at automotive applications. The algorithm is based on the sum of absolute differences (SAD) and computes the disparity map using 320 times 240 input images with a maximum disparity of 100 pixels. The hardware operates at a frequency of 65 MHz and achieves a frame rate of 425 fps by calculating the data highly parallel and pipelined. Thus an implemented and basically optimized software solution, running on an Intel Pentium 4 with 3 GHz clock frequency is 166 times outperformed.

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Cite

Text

Ambrosch et al. "Hardware Implementation of an SAD Based Stereo Vision Algorithm." IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2007. doi:10.1109/CVPR.2007.383417

Markdown

[Ambrosch et al. "Hardware Implementation of an SAD Based Stereo Vision Algorithm." IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2007.](https://mlanthology.org/cvpr/2007/ambrosch2007cvpr-hardware/) doi:10.1109/CVPR.2007.383417

BibTeX

@inproceedings{ambrosch2007cvpr-hardware,
  title     = {{Hardware Implementation of an SAD Based Stereo Vision Algorithm}},
  author    = {Ambrosch, Kristian and Kubinger, Wilfried and Humenberger, Martin and Steininger, Andreas},
  booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition},
  year      = {2007},
  doi       = {10.1109/CVPR.2007.383417},
  url       = {https://mlanthology.org/cvpr/2007/ambrosch2007cvpr-hardware/}
}