ML Anthology

Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms

Daniel Baumgartner, Peter Rössler, Wilfried Kubinger
CVPR 2007
doi:10.1109/CVPR.2007.383421 /cvpr/2007/baumgartner2007cvpr-performance/

Abstract

Selecting an embedded hardware platform for image processing has a big influence on the achievable performance. This paper reports our work on a performance benchmark of different implementations of some low-level vision algorithms. The algorithms are implemented on both Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) high-speed embedded platforms. The target platforms are a TITMS320C6414 DSP and an Altera Stratix FPGA. The implementations are evaluated, compared and discussed. The DSP implementations outperform the FPGA implementations, but at the cost of spending all its resources to these tasks. FPGAs, however, are well suited to algorithms, which benefit from parallel execution.

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Cite

Text

Baumgartner et al. "Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms." IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2007. doi:10.1109/CVPR.2007.383421

Markdown

[Baumgartner et al. "Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms." IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2007.](https://mlanthology.org/cvpr/2007/baumgartner2007cvpr-performance/) doi:10.1109/CVPR.2007.383421

BibTeX

@inproceedings{baumgartner2007cvpr-performance,
  title     = {{Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms}},
  author    = {Baumgartner, Daniel and Rössler, Peter and Kubinger, Wilfried},
  booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition},
  year      = {2007},
  doi       = {10.1109/CVPR.2007.383421},
  url       = {https://mlanthology.org/cvpr/2007/baumgartner2007cvpr-performance/}
}