Expanding Disparity Range in an FPGA Stereo System While Keeping Resource Utilization Low

Abstract

Field Programmable Gate Array devices (FPGAs) are attractive for implementing computer vision algorithms due to the fact that they allow the designer to exploit the parallel nature of many vision algorithms, thus offering substantial speed improvements over fixed hardware/software systems. One major drawback, however, is that adding resources to reconfigurable devices is not as simple as adding memory or upgrading a hard disk. This becomes a problem when adapting a system to deal with larger image sizes or, in the case of stereo disparity estimation, larger disparity ranges (parameter ranges in general). This paper describes preliminary work on a design to expand the disparity range and input image size of an existing FPGA-based stereo system [8] while not significantly expanding resource requirements. Simulations on synthetic and real images are given, as well as a description of the proposed architecture changes in porting the system to a newer FPGA architecture.