An FPGA-Based Verification Framework for Real-Time Vision Systems
Abstract
Field-Programmable Gate Arrays (FPGAs) have become a mainstay in the digital electronics world both for the ease of implementation as well as their inherent usefulness in incrementally refining hardware designs. When moving to an Application Specific Integrated Circuit (ASIC) or System on a Chip (SoC), verification becomes a very time consuming process, with virtually no room for error. As a result, a variety of methods have been devised to decrease the risk when creating an ASIC or SoC. We describe a hardware and software framework for testing real-time vision algorithms for lowering the uncertainty in FPGA and SoC development, while reducing the SoC verification time. The framework benefits from hardware and software verification, ease of reconfiguration for testing multiple vision algorithms, and an iterative hardware/ software co-design.
Cite
Text
van der Wal et al. "An FPGA-Based Verification Framework for Real-Time Vision Systems." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2006. doi:10.1109/CVPRW.2006.27Markdown
[van der Wal et al. "An FPGA-Based Verification Framework for Real-Time Vision Systems." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2006.](https://mlanthology.org/cvprw/2006/vanderwal2006cvprw-fpgabased/) doi:10.1109/CVPRW.2006.27BibTeX
@inproceedings{vanderwal2006cvprw-fpgabased,
title = {{An FPGA-Based Verification Framework for Real-Time Vision Systems}},
author = {van der Wal, Gooitzen S. and Brehm, Frederic and Piacentino, Michael R. and Marakowitz, James and Gudis, Eduardo and Sufi, Azhar A. and Montante, James},
booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops},
year = {2006},
pages = {124},
doi = {10.1109/CVPRW.2006.27},
url = {https://mlanthology.org/cvprw/2006/vanderwal2006cvprw-fpgabased/}
}