ML Anthology

Invited Paper: Adapting Algorithms for Hardware Implementation

Donald G. Bailey
CVPRW 2011 pp. 177-184
doi:10.1109/CVPRW.2011.5981828 /cvprw/2011/bailey2011cvprw-invited/

Abstract

Embedded vision often requires balancing the computation and power requirements of an application. Hardware implementation of the vision algorithm using an FPGA enables parallelism to be exploited, allowing clock speeds to be significantly reduced. However, simply porting software algorithms usually gives disappointing performance. Software algorithms are usually optimised for serial implementation. An efficient FPGA implementation requires transforming the algorithm to make better use of parallelism. Several transformations are illustrated using connected components analysis.

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Cite

Text

Bailey. "Invited Paper: Adapting Algorithms for Hardware Implementation." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2011. doi:10.1109/CVPRW.2011.5981828

Markdown

[Bailey. "Invited Paper: Adapting Algorithms for Hardware Implementation." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2011.](https://mlanthology.org/cvprw/2011/bailey2011cvprw-invited/) doi:10.1109/CVPRW.2011.5981828

BibTeX

@inproceedings{bailey2011cvprw-invited,
  title     = {{Invited Paper: Adapting Algorithms for Hardware Implementation}},
  author    = {Bailey, Donald G.},
  booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops},
  year      = {2011},
  pages     = {177-184},
  doi       = {10.1109/CVPRW.2011.5981828},
  url       = {https://mlanthology.org/cvprw/2011/bailey2011cvprw-invited/}
}