ML Anthology

FPGA Implementation of Naive Bayes Classifier for Visual Object Recognition

Hongying Meng, Kofi Appiah, Andrew Hunter, Patrick Dickinson
CVPRW 2011 pp. 123-128
doi:10.1109/CVPRW.2011.5981831 /cvprw/2011/meng2011cvprw-fpga/

Abstract

In this paper, a Naive Bayes classifier was simplified and implemented as a multi-class classifier for binary feature vectors. It was designed on FPGA using very limited hardware resources and runs quickly and efficiently in both training and testing phases. It was first tested on a handwriting digital number dataset, and then applied in the visual object recognition on a single FPGA based visual surveillance system. It was compared with a binary Self Organizing Map (bSOM) using tri-states operation on FPGA, and the experimental results demonstrated both its higher performance and lower resource usage on the FPGA chip.

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Cite

Text

Meng et al. "FPGA Implementation of Naive Bayes Classifier for Visual Object Recognition." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2011. doi:10.1109/CVPRW.2011.5981831

Markdown

[Meng et al. "FPGA Implementation of Naive Bayes Classifier for Visual Object Recognition." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2011.](https://mlanthology.org/cvprw/2011/meng2011cvprw-fpga/) doi:10.1109/CVPRW.2011.5981831

BibTeX

@inproceedings{meng2011cvprw-fpga,
  title     = {{FPGA Implementation of Naive Bayes Classifier for Visual Object Recognition}},
  author    = {Meng, Hongying and Appiah, Kofi and Hunter, Andrew and Dickinson, Patrick},
  booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops},
  year      = {2011},
  pages     = {123-128},
  doi       = {10.1109/CVPRW.2011.5981831},
  url       = {https://mlanthology.org/cvprw/2011/meng2011cvprw-fpga/}
}