ML Anthology

Feature Detection and Matching on an SIMD/MIMD Hybrid Embedded Processor

Alejandro Nieto, David López Vilariño, Víctor M. Brea
CVPRW 2012 pp. 21-26
doi:10.1109/CVPRW.2012.6238890 /cvprw/2012/nieto2012cvprw-feature/

Abstract

This work presents the implementation of a feature detection and matching algorithm on an innovative SIMD/MIMD dynamically-reconfigurable architecture intended for high-performance embedded vision systems. An FPGA-based system-on-chip with a 128-unit coprocessor running at 150 MHz is able to locate a target in 320 × 240 px images in less than 1 ms. It is also shown how to map the algorithms to speedup the processing taking advantage of the different available computation modes.

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Cite

Text

Nieto et al. "Feature Detection and Matching on an SIMD/MIMD Hybrid Embedded Processor." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2012. doi:10.1109/CVPRW.2012.6238890

Markdown

[Nieto et al. "Feature Detection and Matching on an SIMD/MIMD Hybrid Embedded Processor." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2012.](https://mlanthology.org/cvprw/2012/nieto2012cvprw-feature/) doi:10.1109/CVPRW.2012.6238890

BibTeX

@inproceedings{nieto2012cvprw-feature,
  title     = {{Feature Detection and Matching on an SIMD/MIMD Hybrid Embedded Processor}},
  author    = {Nieto, Alejandro and Vilariño, David López and Brea, Víctor M.},
  booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops},
  year      = {2012},
  pages     = {21-26},
  doi       = {10.1109/CVPRW.2012.6238890},
  url       = {https://mlanthology.org/cvprw/2012/nieto2012cvprw-feature/}
}