FPGA-Based Real-Time Pedestrian Detection on High-Resolution Images
Abstract
This paper focuses on real-time pedestrian detection on Field Programmable Gate Arrays (FPGAs) using the Histograms of Oriented Gradients (HOG) descriptor in combination with a Support Vector Machine (SVM) for classification as a basic method. We propose to process image data at twice the pixel frequency and to normalize blocks with the L1-Sqrt-norm resulting in an efficient resource utilization. This implementation allows for parallel computation of different scales. Combined with a time-multiplex approach we increase multiscale capabilities beyond resource limitations. We are able to process 64 high resolution images (1920 × 1080 pixels) per second at 18 scales with a latency of less than 150 u s. 1.79 million HOG descriptors and their SVM classifications can be calculated per second and per scale, which outperforms current FPGA implementations by a factor of 4.
Cite
Text
Hahnle et al. "FPGA-Based Real-Time Pedestrian Detection on High-Resolution Images." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2013. doi:10.1109/CVPRW.2013.95Markdown
[Hahnle et al. "FPGA-Based Real-Time Pedestrian Detection on High-Resolution Images." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2013.](https://mlanthology.org/cvprw/2013/hahnle2013cvprw-fpgabased/) doi:10.1109/CVPRW.2013.95BibTeX
@inproceedings{hahnle2013cvprw-fpgabased,
title = {{FPGA-Based Real-Time Pedestrian Detection on High-Resolution Images}},
author = {Hahnle, Michael and Saxen, Frerk and Hisung, Matthias and Brunsmann, Ulrich and Doll, Konrad},
booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops},
year = {2013},
pages = {629-635},
doi = {10.1109/CVPRW.2013.95},
url = {https://mlanthology.org/cvprw/2013/hahnle2013cvprw-fpgabased/}
}