A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform

Eibensteiner et al. "A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2014. doi:10.1109/CVPRW.2014.97

[Eibensteiner et al. "A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2014.](https://mlanthology.org/cvprw/2014/eibensteiner2014cvprw-highperformance/) doi:10.1109/CVPRW.2014.97

@inproceedings{eibensteiner2014cvprw-highperformance,
  title     = {{A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform}},
  author    = {Eibensteiner, Florian and Kogler, Jürgen and Scharinger, Josef},
  booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops},
  year      = {2014},
  pages     = {637-644},
  doi       = {10.1109/CVPRW.2014.97},
  url       = {https://mlanthology.org/cvprw/2014/eibensteiner2014cvprw-highperformance/}
}