FPGA Acceleration for Feature Based Processing Applications
Abstract
Feature based vision applications rely on highly efficient extraction and analysis of features from images to reach satisfactory levels of performance and latency. In this paper, we describe the implementation of an algorithm that combines distributed feature detector (D-HCD) with a rotational invariant feature descriptor (R-HOG). Based on an algorithmic comparison with other feature detectors and descriptors, we show that our algorithms have the lowest error rate for 3D aerial scene matching. We present implementation on a low-cost Zynq FPGA that achieves 15x speedup, 5x reduction in latency over a quad core CPU. Our results show the considerable promise of our proposed implementation for fast and efficient robotic and aerial drone / UAV applications.
Cite
Text
van der Wal et al. "FPGA Acceleration for Feature Based Processing Applications." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2015. doi:10.1109/CVPRW.2015.7301365Markdown
[van der Wal et al. "FPGA Acceleration for Feature Based Processing Applications." IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2015.](https://mlanthology.org/cvprw/2015/vanderwal2015cvprw-fpga/) doi:10.1109/CVPRW.2015.7301365BibTeX
@inproceedings{vanderwal2015cvprw-fpga,
title = {{FPGA Acceleration for Feature Based Processing Applications}},
author = {van der Wal, Gooitzen S. and Zhang, David C. and Kandaswamy, Indu and Marakowitz, James and Kaighn, Kevin and Zhang, Joe and Chai, Sek M.},
booktitle = {IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops},
year = {2015},
pages = {42-47},
doi = {10.1109/CVPRW.2015.7301365},
url = {https://mlanthology.org/cvprw/2015/vanderwal2015cvprw-fpga/}
}