A Bit Plane Architecture for an Image Analysis Processor Implemented with P.L.C.A. Gate Array
Abstract
As Image Analysis resorts to increasingly powerful algorithms, the processing time is correspondingly extended. Consequently, system designers are constantly looking for new technologies and new architectures capable of improving processing speed without increasing the complexity and the cost of the machines. To achieve this objective, the Centre de Morphologie Mathématique (Ecole des Mines de Paris) has designed and developed, a new image processor for Mathematical Morphology based on Programmable Logic Cell Array (PLCA) technology. This processor, incorporated into the Cambridge Instruments Quantimet 570, is capable of performing complex morphological transformations on 512 × 512 images of 8 bits per pixel at the rate of 27 msec per image. This speed, associated with extensive algorithmic software support, makes it an extremely powerful tool in the field of image analysis.
Cite
Text
Klein et al. "A Bit Plane Architecture for an Image Analysis Processor Implemented with P.L.C.A. Gate Array." European Conference on Computer Vision, 1990. doi:10.1007/BFB0014848Markdown
[Klein et al. "A Bit Plane Architecture for an Image Analysis Processor Implemented with P.L.C.A. Gate Array." European Conference on Computer Vision, 1990.](https://mlanthology.org/eccv/1990/klein1990eccv-bit/) doi:10.1007/BFB0014848BibTeX
@inproceedings{klein1990eccv-bit,
title = {{A Bit Plane Architecture for an Image Analysis Processor Implemented with P.L.C.A. Gate Array}},
author = {Klein, Jean-Claude and Collange, François and Bilodeau, Michel},
booktitle = {European Conference on Computer Vision},
year = {1990},
pages = {33-49},
doi = {10.1007/BFB0014848},
url = {https://mlanthology.org/eccv/1990/klein1990eccv-bit/}
}