Efficient Systolic Architecture and Power Modeling for Finite Ridgelet Transform
Abstract
In this paper, an efficient architecture for the finite ridgelet transform (FRIT) suitable for embedded computer vision systems based on a parallel, systolic finite radon transform (FRAT) sub-block and Haar wavelet transform (HWT) block is presented. Field programmable gate array (FPGA) implementation is carried out to characterise the performance of the proposed FRIT architecture. Additionally, a high level power macromodeling and analysis methodology that enables accurate characterisation of power consumption as a function of various design and performance metrics is presented. The mathematical models that are derived allow the system designer to make intelligent trade-offs when incorporating the developed cores as sub-blocks in hardware based image and video processing systems.
Cite
Text
Sazish et al. "Efficient Systolic Architecture and Power Modeling for Finite Ridgelet Transform." IEEE/CVF International Conference on Computer Vision Workshops, 2009. doi:10.1109/ICCVW.2009.5457619Markdown
[Sazish et al. "Efficient Systolic Architecture and Power Modeling for Finite Ridgelet Transform." IEEE/CVF International Conference on Computer Vision Workshops, 2009.](https://mlanthology.org/iccvw/2009/sazish2009iccvw-efficient/) doi:10.1109/ICCVW.2009.5457619BibTeX
@inproceedings{sazish2009iccvw-efficient,
title = {{Efficient Systolic Architecture and Power Modeling for Finite Ridgelet Transform}},
author = {Sazish, Abdul Naser and Chandrasekaran, Shrutisagar and Amira, Abbes},
booktitle = {IEEE/CVF International Conference on Computer Vision Workshops},
year = {2009},
pages = {821-827},
doi = {10.1109/ICCVW.2009.5457619},
url = {https://mlanthology.org/iccvw/2009/sazish2009iccvw-efficient/}
}