Constraint Posting for Verifying VLSI Circuits

Abstract

We apply constraint posting to the problem of reasoning about from structure. Constraint posting is a technique used by some planners to coordinate decisions. At each decision point constraints are posted that later decisions must obey. We use constraint posting to help verify that a circuit modelled at the analog level will exhibit its intended digital behavior. A circuit's analog behavior depends not only on the circuit's but also on how the circuit is used. We post constraints to ensure that a circuit will only be used commensurate with its intended function. This research shows that while there is no function from structure, there is from structure and constraint posting. We have implemented these ideas in program that rapidly verifies large circuits.