Temporal Planning for Compilation of Quantum Approximate Optimization Circuits
Abstract
We investigate the application of temporal planners to the problem of compiling quantum circuits to emerging quantum hardware. While our approach is general, we focus our initial experiments on Quantum Approximate Optimization Algorithm (QAOA) circuits that have few ordering constraints and thus allow highly parallel plans. We report on experiments using several temporal planners to compile circuits of various sizes to a realistic hardware architecture. This early empirical evaluation suggests that temporal planning is a viable approach to quantum circuit compilation.
Cite
Text
Venturelli et al. "Temporal Planning for Compilation of Quantum Approximate Optimization Circuits." International Joint Conference on Artificial Intelligence, 2017. doi:10.24963/IJCAI.2017/620Markdown
[Venturelli et al. "Temporal Planning for Compilation of Quantum Approximate Optimization Circuits." International Joint Conference on Artificial Intelligence, 2017.](https://mlanthology.org/ijcai/2017/venturelli2017ijcai-temporal/) doi:10.24963/IJCAI.2017/620BibTeX
@inproceedings{venturelli2017ijcai-temporal,
title = {{Temporal Planning for Compilation of Quantum Approximate Optimization Circuits}},
author = {Venturelli, Davide and Do, Minh and Rieffel, Eleanor Gilbert and Frank, Jeremy},
booktitle = {International Joint Conference on Artificial Intelligence},
year = {2017},
pages = {4440-4446},
doi = {10.24963/IJCAI.2017/620},
url = {https://mlanthology.org/ijcai/2017/venturelli2017ijcai-temporal/}
}