VLSI Implementation of Neural Classifiers
Abstract
The embedding of neural networks in real-time systems performing classification and clustering tasks requires that models be implemented in hardware. A flexible, pipelined associative memory capable of operating in real-time is proposed as a hardware substrate for the emulation of neural fixed-radius clustering and binary classification schemes. This paper points out several important considerations in the development of hardware implementations. As a specific example, it is shown how the ART1 paradigm can be functionally emulated by the limited resolution pipelined architecture, in the absence of full parallelism.
Cite
Text
Rao et al. "VLSI Implementation of Neural Classifiers." Neural Computation, 1990. doi:10.1162/NECO.1990.2.1.35Markdown
[Rao et al. "VLSI Implementation of Neural Classifiers." Neural Computation, 1990.](https://mlanthology.org/neco/1990/rao1990neco-vlsi/) doi:10.1162/NECO.1990.2.1.35BibTeX
@article{rao1990neco-vlsi,
title = {{VLSI Implementation of Neural Classifiers}},
author = {Rao, Arun and Walker, Mark R. and Clark, Lawrence T. and Akers, Lex A. and Grondin, Robert O.},
journal = {Neural Computation},
year = {1990},
pages = {35-43},
doi = {10.1162/NECO.1990.2.1.35},
volume = {2},
url = {https://mlanthology.org/neco/1990/rao1990neco-vlsi/}
}