Bit-Serial Neural Networks
Abstract
A bit - serial VLSI neural network is described from an initial architecture for a synapse array through to silicon layout and board design. The issues surrounding bit - serial computation, and analog/digital arithmetic are discussed and the parallel development of a hybrid analog/digital neural network is outlined. Learning and recall capabilities are reported for the bit - serial network along with a projected specification for a 64 - neuron, bit - serial board operating at 20 MHz. This tech(cid:173) nique is extended to a 256 (2562 synapses) network with an update time of 3ms, using a "paging" technique to time - multiplex calculations through the synapse array.
Cite
Text
Murray et al. "Bit-Serial Neural Networks." Neural Information Processing Systems, 1987.Markdown
[Murray et al. "Bit-Serial Neural Networks." Neural Information Processing Systems, 1987.](https://mlanthology.org/neurips/1987/murray1987neurips-bitserial/)BibTeX
@inproceedings{murray1987neurips-bitserial,
title = {{Bit-Serial Neural Networks}},
author = {Murray, Alan F. and Smith, Anthony V. W. and Butler, Zoe F.},
booktitle = {Neural Information Processing Systems},
year = {1987},
pages = {573-583},
url = {https://mlanthology.org/neurips/1987/murray1987neurips-bitserial/}
}