An Analog VLSI Chip for Thin-Plate Surface Interpolation
Abstract
Reconstructing a surface from sparse sensory data is a well-known problem iIi computer vision. This paper describes an experimental analog VLSI chip for smooth surface interpolation from sparse depth data. An eight-node ID network was designed in 3J.lm CMOS and successfully tested. The network minimizes a second-order or "thin(cid:173) plate" energy of the surface. The circuit directly implements the cou(cid:173) pled depth/slope model of surface reconstruction (Harris, 1987). In addition, this chip can provide Gaussian-like smoothing of images.
Cite
Text
Harris. "An Analog VLSI Chip for Thin-Plate Surface Interpolation." Neural Information Processing Systems, 1988.Markdown
[Harris. "An Analog VLSI Chip for Thin-Plate Surface Interpolation." Neural Information Processing Systems, 1988.](https://mlanthology.org/neurips/1988/harris1988neurips-analog/)BibTeX
@inproceedings{harris1988neurips-analog,
title = {{An Analog VLSI Chip for Thin-Plate Surface Interpolation}},
author = {Harris, John G.},
booktitle = {Neural Information Processing Systems},
year = {1988},
pages = {687-694},
url = {https://mlanthology.org/neurips/1988/harris1988neurips-analog/}
}