ML Anthology

A Low-Power CMOS Circuit Which Emulates Temporal Electrical Properties of Neurons

Jack L. Meador, Clint S. Cole
NeurIPS 1988 pp. 678-686
/neurips/1988/meador1988neurips-lowpower/

Abstract

This paper describes a CMOS artificial neuron. The circuit is directly derived from the voltage-gated channel model of neural membrane, has low power dissipation, and small layout geometry. The principal motivations behind this work include a desire for high performance, more accurate neuron emulation, and the need for higher density in practical neural network implementations.

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Cite

Text

Meador and Cole. "A Low-Power CMOS Circuit Which Emulates Temporal Electrical Properties of Neurons." Neural Information Processing Systems, 1988.

Markdown

[Meador and Cole. "A Low-Power CMOS Circuit Which Emulates Temporal Electrical Properties of Neurons." Neural Information Processing Systems, 1988.](https://mlanthology.org/neurips/1988/meador1988neurips-lowpower/)

BibTeX

@inproceedings{meador1988neurips-lowpower,
  title     = {{A Low-Power CMOS Circuit Which Emulates Temporal Electrical Properties of Neurons}},
  author    = {Meador, Jack L. and Cole, Clint S.},
  booktitle = {Neural Information Processing Systems},
  year      = {1988},
  pages     = {678-686},
  url       = {https://mlanthology.org/neurips/1988/meador1988neurips-lowpower/}
}