VLSI Implementation of a High-Capacity Neural Network Associative Memory
Abstract
In this paper we describe the VLSI design and testing of a high capacity associative memory which we call the exponential cor(cid:173) relation associative memory (ECAM). The prototype 3J.'-CMOS programmable chip is capable of storing 32 memory patterns of 24 bits each. The high capacity of the ECAM is partly due to the use of special exponentiation neurons, which are implemented via sub-threshold MOS transistors in this design. The prototype chip is capable of performing one associative recall in 3 J.'S.
Cite
Text
Chiueh and Goodman. "VLSI Implementation of a High-Capacity Neural Network Associative Memory." Neural Information Processing Systems, 1989.Markdown
[Chiueh and Goodman. "VLSI Implementation of a High-Capacity Neural Network Associative Memory." Neural Information Processing Systems, 1989.](https://mlanthology.org/neurips/1989/chiueh1989neurips-vlsi/)BibTeX
@inproceedings{chiueh1989neurips-vlsi,
title = {{VLSI Implementation of a High-Capacity Neural Network Associative Memory}},
author = {Chiueh, Tzi-Dar and Goodman, Rodney M.},
booktitle = {Neural Information Processing Systems},
year = {1989},
pages = {793-800},
url = {https://mlanthology.org/neurips/1989/chiueh1989neurips-vlsi/}
}