ML Anthology

VLSI Implementation of TInMANN

Matt Melton, Tan Phan, Doug Reeves, Dave Van den Bout
NeurIPS 1990 pp. 1046-1052
/neurips/1990/melton1990neurips-vlsi/

Abstract

A massively parallel, all-digital, stochastic architecture - TlnMAN N - is described which performs competitive and Kohonen types of learning. A VLSI design is shown for a TlnMANN neuron which fits within a small, inexpensive MOSIS TinyChip frame, yet which can be used to build larger networks of several hundred neurons. The neuron operates at a speed of 15 MHz which allows the network to process 290,000 training examples per second. Use of level sensitive scan logic provides the chip with 100% fault coverage, permitting very reliable neural systems to be built.

PDF NeurIPS Semantic Scholar

Cite

Text

Melton et al. "VLSI Implementation of TInMANN." Neural Information Processing Systems, 1990.

Markdown

[Melton et al. "VLSI Implementation of TInMANN." Neural Information Processing Systems, 1990.](https://mlanthology.org/neurips/1990/melton1990neurips-vlsi/)

BibTeX

@inproceedings{melton1990neurips-vlsi,
  title     = {{VLSI Implementation of TInMANN}},
  author    = {Melton, Matt and Phan, Tan and Reeves, Doug and Van den Bout, Dave},
  booktitle = {Neural Information Processing Systems},
  year      = {1990},
  pages     = {1046-1052},
  url       = {https://mlanthology.org/neurips/1990/melton1990neurips-vlsi/}
}