Digital Boltzmann VLSI for Constraint Satisfaction and Learning
Abstract
We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 108 con(cid:173) nection updates/sec; recall is 12000 patterns/sec for typical condi(cid:173) tions. The chip's high speed is due to parallel computation of inner products, limited (but adequate) precision for weights and activa(cid:173) tions (5 bits), fast clock (125 MHz), and several design insights.
Cite
Text
Murray et al. "Digital Boltzmann VLSI for Constraint Satisfaction and Learning." Neural Information Processing Systems, 1993.Markdown
[Murray et al. "Digital Boltzmann VLSI for Constraint Satisfaction and Learning." Neural Information Processing Systems, 1993.](https://mlanthology.org/neurips/1993/murray1993neurips-digital/)BibTeX
@inproceedings{murray1993neurips-digital,
title = {{Digital Boltzmann VLSI for Constraint Satisfaction and Learning}},
author = {Murray, Michael and Leung, Ming-Tak and Boonyanit, Kan and Kritayakirana, Kong and Burg, James B. and Wolff, Gregory J. and Watanabe, Tokahiro and Schwartz, Edward and Stork, David G. and Peterson, Allen M.},
booktitle = {Neural Information Processing Systems},
year = {1993},
pages = {896-903},
url = {https://mlanthology.org/neurips/1993/murray1993neurips-digital/}
}