A Charge-Based CMOS Parallel Analog Vector Quantizer

NeurIPS 1994 pp. 779-786

/neurips/1994/cauwenberghs1994neurips-chargebased/

Abstract

We present an analog VLSI chip for parallel analog vector quantiza(cid:173) tion. The MOSIS 2.0 J..Lm double-poly CMOS Tiny chip contains an array of 16 x 16 charge-based distance estimation cells, implementing a mean absolute difference (MAD) metric operating on a 16-input analog vector field and 16 analog template vectors. The distance cell includ(cid:173) ing dynamic template storage measures 60 x 78 J..Lm2 • Additionally, the chip features a winner-take-all (WTA) output circuit of linear com(cid:173) plexity, with global positive feedback for fast and decisive settling of a single winner output. Experimental results on the complete 16 x 16 VQ system demonstrate correct operation with 34 dB analog input dynamic range and 3 J..Lsec cycle time at 0.7 mW power dissipation.

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Text

Cauwenberghs and Pedroni. "A Charge-Based CMOS Parallel Analog Vector Quantizer." Neural Information Processing Systems, 1994.

Markdown

[Cauwenberghs and Pedroni. "A Charge-Based CMOS Parallel Analog Vector Quantizer." Neural Information Processing Systems, 1994.](https://mlanthology.org/neurips/1994/cauwenberghs1994neurips-chargebased/)

BibTeX

@inproceedings{cauwenberghs1994neurips-chargebased,
  title     = {{A Charge-Based CMOS Parallel Analog Vector Quantizer}},
  author    = {Cauwenberghs, Gert and Pedroni, Volnei},
  booktitle = {Neural Information Processing Systems},
  year      = {1994},
  pages     = {779-786},
  url       = {https://mlanthology.org/neurips/1994/cauwenberghs1994neurips-chargebased/}
}