The Ni1000: High Speed Parallel VLSI for Implementing Multilayer Perceptrons
Abstract
In this paper we present a new version of the standard multilayer perceptron (MLP) algorithm for the state-of-the-art in neural net(cid:173) work VLSI implementations: the Intel Ni1000. This new version of the MLP uses a fundamental property of high dimensional spaces which allows the 12-norm to be accurately approximated by the It -norm. This approach enables the standard MLP to utilize the parallel architecture of the Ni1000 to achieve on the order of 40000, 256-dimensional classifications per second.
Cite
Text
Perrone and Cooper. "The Ni1000: High Speed Parallel VLSI for Implementing Multilayer Perceptrons." Neural Information Processing Systems, 1994.Markdown
[Perrone and Cooper. "The Ni1000: High Speed Parallel VLSI for Implementing Multilayer Perceptrons." Neural Information Processing Systems, 1994.](https://mlanthology.org/neurips/1994/perrone1994neurips-ni1000/)BibTeX
@inproceedings{perrone1994neurips-ni1000,
title = {{The Ni1000: High Speed Parallel VLSI for Implementing Multilayer Perceptrons}},
author = {Perrone, Michael P. and Cooper, Leon N.},
booktitle = {Neural Information Processing Systems},
year = {1994},
pages = {747-754},
url = {https://mlanthology.org/neurips/1994/perrone1994neurips-ni1000/}
}