Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning
Abstract
Experimental data has shown that synaptic strength modification in some types of biological neurons depends upon precise spike tim(cid:173) ing differences between presynaptic and postsynaptic spikes. Sev(cid:173) eral temporally-asymmetric Hebbian learning rules motivated by this data have been proposed. We argue that such learning rules are suitable to analog VLSI implementation. We describe an eas(cid:173) ily tunable circuit to modify the weight of a silicon spiking neuron according to those learning rules. Test results from the fabrication of the circuit using a O.6J.lm CMOS process are given.
Cite
Text
Bofill et al. "Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning." Neural Information Processing Systems, 2001.Markdown
[Bofill et al. "Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning." Neural Information Processing Systems, 2001.](https://mlanthology.org/neurips/2001/bofill2001neurips-citcuits/)BibTeX
@inproceedings{bofill2001neurips-citcuits,
title = {{Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning}},
author = {Bofill, A. and Thompson, D. P. and Murray, Alan F.},
booktitle = {Neural Information Processing Systems},
year = {2001},
pages = {1091-1098},
url = {https://mlanthology.org/neurips/2001/bofill2001neurips-citcuits/}
}