Analog Soft-Pattern-Matching Classifier Using Floating-Gate MOS Technology
Abstract
A flexible pattern-matching analog classifier is presented in con- junction with a robust image representation algorithm called Prin- cipal Axes Projection (PAP). In the circuit, the functional form of matching is configurable in terms of the peak position, the peak height and the sharpness of the similarity evaluation. The test chip was fabri- cated in a 0.6-m m CMOS technology and successfully applied to hand-written pattern recognition and medical radiograph analysis using PAP as a feature extraction pre-processing step for robust image coding. The separation and classification of overlapping patterns is also ex- perimentally demonstrated.
Cite
Text
Yamasaki and Shibata. "Analog Soft-Pattern-Matching Classifier Using Floating-Gate MOS Technology." Neural Information Processing Systems, 2001.Markdown
[Yamasaki and Shibata. "Analog Soft-Pattern-Matching Classifier Using Floating-Gate MOS Technology." Neural Information Processing Systems, 2001.](https://mlanthology.org/neurips/2001/yamasaki2001neurips-analog/)BibTeX
@inproceedings{yamasaki2001neurips-analog,
title = {{Analog Soft-Pattern-Matching Classifier Using Floating-Gate MOS Technology}},
author = {Yamasaki, Toshihiko and Shibata, Tadashi},
booktitle = {Neural Information Processing Systems},
year = {2001},
pages = {1131-1138},
url = {https://mlanthology.org/neurips/2001/yamasaki2001neurips-analog/}
}