A Summating, Exponentially-Decaying CMOS Synapse for Spiking Neural Systems
Abstract
Synapses are a critical element of biologically-realistic, spike-based neu- ral computation, serving the role of communication, computation, and modification. Many different circuit implementations of synapse func- tion exist with different computational goals in mind. In this paper we describe a new CMOS synapse design that separately controls quiescent leak current, synaptic gain, and time-constant of decay. This circuit im- plements part of a commonly-used kinetic model of synaptic conduc- tance. We show a theoretical analysis and experimental data for proto- types fabricated in a commercially-available 1.5µm CMOS process.
Cite
Text
Shi and Horiuchi. "A Summating, Exponentially-Decaying CMOS Synapse for Spiking Neural Systems." Neural Information Processing Systems, 2003.Markdown
[Shi and Horiuchi. "A Summating, Exponentially-Decaying CMOS Synapse for Spiking Neural Systems." Neural Information Processing Systems, 2003.](https://mlanthology.org/neurips/2003/shi2003neurips-summating/)BibTeX
@inproceedings{shi2003neurips-summating,
title = {{A Summating, Exponentially-Decaying CMOS Synapse for Spiking Neural Systems}},
author = {Shi, Rock Z. and Horiuchi, Timothy K.},
booktitle = {Neural Information Processing Systems},
year = {2003},
pages = {1003-1010},
url = {https://mlanthology.org/neurips/2003/shi2003neurips-summating/}
}