On-Chip Compensation of Device-Mismatch Effects in Analog VLSI Neural Networks
Abstract
Device mismatch in VLSI degrades the accuracy of analog arithmetic circuits and lowers the learning performance of large-scale neural net- works implemented in this technology. We show compact, low-power on-chip calibration techniques that compensate for device mismatch. Our techniques enable large-scale analog VLSI neural networks with learn- ing performance on the order of 10 bits. We demonstrate our techniques on a 64-synapse linear perceptron learning with the Least-Mean-Squares (LMS) algorithm, and fabricated in a 0.35m CMOS process.
Cite
Text
Figueroa et al. "On-Chip Compensation of Device-Mismatch Effects in Analog VLSI Neural Networks." Neural Information Processing Systems, 2004.Markdown
[Figueroa et al. "On-Chip Compensation of Device-Mismatch Effects in Analog VLSI Neural Networks." Neural Information Processing Systems, 2004.](https://mlanthology.org/neurips/2004/figueroa2004neurips-onchip/)BibTeX
@inproceedings{figueroa2004neurips-onchip,
title = {{On-Chip Compensation of Device-Mismatch Effects in Analog VLSI Neural Networks}},
author = {Figueroa, Miguel and Bridges, Seth and Diorio, Chris},
booktitle = {Neural Information Processing Systems},
year = {2004},
pages = {441-448},
url = {https://mlanthology.org/neurips/2004/figueroa2004neurips-onchip/}
}