An Analog Visual Pre-Processing Processor Employing Cyclic Line Access in Only-Nearest-Neighbor-Interconnects Architecture
Abstract
An analog focal-plane processor having a 128128 photodiode array has been developed for directional edge filtering. It can perform 44-pixel kernel convolution for entire pixels only with 256 steps of simple ana- log processing. Newly developed cyclic line access and row-parallel processing scheme in conjunction with the “only-nearest-neighbor in- terconnects” architecture has enabled a very simple implementation. A proof-of-concept chip was fabricated in a 0.35-(cid:0)m 2-poly 3-metal CMOS technology and the edge filtering at a rate of 200 frames/sec. has been experimentally demonstrated.
Cite
Text
Nakashita et al. "An Analog Visual Pre-Processing Processor Employing Cyclic Line Access in Only-Nearest-Neighbor-Interconnects Architecture." Neural Information Processing Systems, 2005.Markdown
[Nakashita et al. "An Analog Visual Pre-Processing Processor Employing Cyclic Line Access in Only-Nearest-Neighbor-Interconnects Architecture." Neural Information Processing Systems, 2005.](https://mlanthology.org/neurips/2005/nakashita2005neurips-analog/)BibTeX
@inproceedings{nakashita2005neurips-analog,
title = {{An Analog Visual Pre-Processing Processor Employing Cyclic Line Access in Only-Nearest-Neighbor-Interconnects Architecture}},
author = {Nakashita, Yusuke and Mita, Yoshio and Shibata, Tadashi},
booktitle = {Neural Information Processing Systems},
year = {2005},
pages = {971-978},
url = {https://mlanthology.org/neurips/2005/nakashita2005neurips-analog/}
}