Fast Channel Simulation via Error-Correcting Codes

Abstract

We consider the design of practically-implementable schemes for the task of channel simulation. Existing methods do not scale with the number of simultaneous uses of the channel and are therefore unable to harness the amortization gains associated with simulating many uses of the channel at once. We show how techniques from the theory of error-correcting codes can be applied to achieve scalability and hence improved performance. As an exemplar, we focus on how polar codes can be used to efficiently simulate i.i.d. copies of a class of binary-output channels.

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Cite

Text

Sriramu et al. "Fast Channel Simulation via Error-Correcting Codes." Neural Information Processing Systems, 2024. doi:10.52202/079017-3427

Markdown

[Sriramu et al. "Fast Channel Simulation via Error-Correcting Codes." Neural Information Processing Systems, 2024.](https://mlanthology.org/neurips/2024/sriramu2024neurips-fast/) doi:10.52202/079017-3427

BibTeX

@inproceedings{sriramu2024neurips-fast,
  title     = {{Fast Channel Simulation via Error-Correcting Codes}},
  author    = {Sriramu, Sharang M. and Barsz, Rochelle and Polito, Elizabeth and Wagner, Aaron B.},
  booktitle = {Neural Information Processing Systems},
  year      = {2024},
  doi       = {10.52202/079017-3427},
  url       = {https://mlanthology.org/neurips/2024/sriramu2024neurips-fast/}
}