VeriThoughts: Enabling Automated Verilog Code Generation Using Reasoning and Formal Verification
Abstract
This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees.
Cite
Text
Yubeaton et al. "VeriThoughts: Enabling Automated Verilog Code Generation Using Reasoning and Formal Verification." Advances in Neural Information Processing Systems, 2025.Markdown
[Yubeaton et al. "VeriThoughts: Enabling Automated Verilog Code Generation Using Reasoning and Formal Verification." Advances in Neural Information Processing Systems, 2025.](https://mlanthology.org/neurips/2025/yubeaton2025neurips-verithoughts/)BibTeX
@inproceedings{yubeaton2025neurips-verithoughts,
title = {{VeriThoughts: Enabling Automated Verilog Code Generation Using Reasoning and Formal Verification}},
author = {Yubeaton, Patrick and Nakkab, Andre and Xiao, Weihua and Collini, Luca and Karri, Ramesh and Hegde, Chinmay and Garg, Siddharth},
booktitle = {Advances in Neural Information Processing Systems},
year = {2025},
url = {https://mlanthology.org/neurips/2025/yubeaton2025neurips-verithoughts/}
}