Explainable Error Detection in Integrated Circuits Image Segmentation via Graph Neural Networks

Abstract

Automated segmentation of integrated circuit (IC) images plays a critical role in hardware assurance, yet remains challenging due to nanoscale structural complexity, extremely low error tolerance, and the limited interpretability of existing deep learning–based approaches. Most convolutional neural network (CNN)–based error detection methods operate at the whole-image level, making it difficult to localize specific faults or explain their structural causes. In this work, we propose an explainable graph neural network (GNN) framework for component-level error detection in IC segmentation masks. Each connected component in the binary mask is converted into a feature-annotated graph that captures both topological connectivity and geometric properties. Error detection is then formulated as graph-based classification, enabling the identification of anomalous components and precise localization of erroneous regions. Experiments on multiple IC layouts under diverse imaging conditions demonstrate that the proposed method achieves robust and generalizable performance. In addition to accurate detection, the graph-based formulation provides improved interpretability by explicitly linking predictions to structural deviations at the component level.